The present invention relates generally to microelectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation. For example, a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror. One manner of accomplishing this is to connect each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source. In this regard, the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
As may be appreciated, sometimes one of the lines needs to cross the other lines in the interconnect bus in order to connect the line to its associated MEM device. For example, where mirrors are fabricated on both sides of the interconnect bus, a line on one side of the bus may need to be connected to an actuator associated with a mirror on the other side of the interconnect bus, or an interior line may need to be connected to an actuator associated with a mirror on either side of the bus. Where the lines of the interconnect bus are fabricated in the lowest level of electrically conductive material on the MEM chip, then the line must cross above the other interconnect bus.
At the scale of typical MEMS devices, there are several considerations associated with crossing one signal carrying line above the other lines of an interconnect bus. Since the crossing line is only a few microns above the other lines of the interconnect bus, the crossing line may be pulled down into undesirable contact with the other lines due to capillary forces during wet chemistry fabrication process steps or by electrostatic attractive forces during operation of the MEMS device. Also, stray particles on the surface of the MEMS chip may become wedged between the crossing line and the other interconnect bus lines below causing a short circuit. Further, undesirable cross-talk may occur between the crossing line and one or more of the other interconnect bus lines being crossed.
Accordingly, the present invention provides a shielded interconnect bus crossover for MEMS and a method for fabricating such an interconnect bus crossover having one or more electrically conductive lines that cross above one or more other electrically conductive lines of the interconnect bus. The line(s) of the shielded interconnect bus crossover is/are both physically and electrically isolated from the interconnect bus lines being crossed over by supporting the crossover line(s) with strategically located support columns and surrounding the crossover line(s) with a surrounding shield structure. The support columns prevent the crossover line(s) from being pulled down against the line(s) being crossed. The surrounding shield structure substantially reduces the possibility of cross-talk between the elevated crossing line(s) and the other interconnect bus lines and alleviates the possibility of short circuits due to particles and the like getting wedged between the crossover line(s) and the other interconnect bus lines.
According to one aspect of the present invention, a shielded interconnect bus crossover includes a substrate and first, second, and third layers of electrically conductive material overlying and supported by at least a portion of the substrate. In this regard, the first, second and third layers may, for example, be comprised of doped polysilicon. In one embodiment, the second layer is comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon. The substrate may, for example, be comprised of silicon. There may also be one or more intervening layers of electrically conductive material and/or dielectric layers between an upper surface of the substrate and the first electrically conductive layer. For example, in one embodiment, there is a dielectric stack comprised of a lower layer of thermal oxide and an upper layer of silicon nitride between the upper surface of the substrate and the first electrically conductive layer.
An interconnect bus is patterned from the first and second layers of electrically conductive material. The interconnect bus includes a plurality of interconnect bus lines, a plurality of interconnect bus shield walls, and an interconnect bus shield supported in a spaced relation above the interconnect bus lines by the interconnect bus shield walls. A plurality of base pads patterned from the first layer of electrically conductive material are positioned at locations within the footprint of the interconnect bus along an imaginary line extending transverse to an orientation of the interconnect bus lines. At least one of the base pads is in contact with at least one of the interconnect bus lines. A plurality of support columns patterned from the second layer of electrically conductive material overlie the base pads and extend vertically upward through holes formed in the interconnect bus shield. At least one elevated crossing line patterned from the third layer of electrically conductive material is supported in a spaced relation above the interconnect bus shield by the support columns. In one embodiment, there may also be at least one crossing line shield wall also patterned from the third layer of electrically conductive material that encircles the elevated crossing line and defines an enclosed area within which the elevated crossing line is located.
Where an additional fourth layer of electrically conductive material is available, there may be an elevated crossing line patterned from the fourth electrically conductive layer on top of the third layer elevated crossing line. In one embodiment, there may also be a crossing line shield wall patterned from the fourth layer of electrically conductive material on top of the third layer crossing line shield wall. The third and fourth layer elevated crossing lines together form a two layer elevated crossing line having enhanced rigidity as compared to a single layer elevated crossing line, which may be desirable to reduce the possibility that the elevated crossing line will be pulled down into undesirable contact with the interconnect bus shield by electrostatic or capillary attractive forces where no sacrificial material remains between the elevated crossing line and the interconnect bus shield. Where there is a lower probability that the crossing line can be pulled down against the interconnect bus shield, such as when a sacrificial material remains between the elevated crossing line and the interconnect bus shield, the interconnect bus crossover may include an electrical/particle shield patterned from the fourth electrically conductive layer that covers the enclosed area defined by the third layer crossing line shield wall. Where a fifth layer of electrically conductive material is available, the interconnect bus crossover may include an electrical/particle shield patterned from the fifth electrically conductive layer that covers the enclosed area defined by the third and fourth layer crossing line shield walls.
According to another aspect of the present invention, a method for making a shielded interconnect bus crossover that crosses at least one interconnect bus line of an interconnect bus over other interconnect lines of the interconnect bus includes the step of depositing a first layer of electrically conductive material (e.g., doped polysilicon) above at least a portion of a substrate. A plurality of base pads are formed from the first layer of electrically conductive material. In this regard, the base pads are formed at various locations within the footprint of the interconnect bus along an imaginary line extending transverse to an orientation of the interconnect bus lines with at least one of the base pads contacting at least one of the interconnect bus lines. A second layer of electrically conductive material (e.g., doped polysilicon) is deposited above the first layer of electrically conductive material. In this regard, there may be an intervening layer of sacrificial material deposited between the first and second electrically conductive layers. In one embodiment, the step of depositing a second layer of electrically conductive material comprises the steps of depositing a lower layer of doped polysilicon, depositing an intervening layer of sacrificial material, removing the intervening layer of sacrificial material, and depositing an upper layer of doped polysilicon, with the lower and upper layers together forming a single layer (i.e., the second layer) of electrically conductive material. After the second layer of electrically conductive material is deposited, a plurality of support columns are formed from the second layer of electrically conductive material. In this regard the support columns are formed to overlie the base pads and extend vertically upward therefrom through holes formed in the interconnect bus shield.
With the support columns formed in the second layer of electrically conductive material, a third layer of electrically conductive material (e.g., doped polysilicon) is deposited above the second layer of electrically conductive material. In this regard, there may be an intervening layer of sacrificial material deposited between the second and third layers of electrically conductive material. At least one elevated crossing line is formed from the third layer of electrically conductive material. In this regard, the elevated crossing line is formed to be supported in a spaced relation above the interconnect bus shield by the support columns. If desired, at least one crossing line shield wall may also be formed from the third layer of electrically conductive material. In this regard, the crossing line shield wall is formed to define an enclosed area within which the third layer elevated crossing line is located.
Where an elevated crossing line with enhanced rigidity is desired, the method of the present invention may also include the additional steps of depositing a fourth layer of electrically conductive material (e.g., doped polysilicon) above the third layer of electrically conductive material and forming at least one elevated crossing line from the fourth layer of electrically conductive material. In this regard, the elevated crossing line formed from the fourth layer of electrically conductive material is formed to overlie the elevated crossing line formed from the third layer of electrically conductive material such that the third and fourth layer elevated crossing lines together form a two layer elevated crossing line. If desired, there may also be the further step of forming at least one crossing line shield wall from the fourth layer of electrically conductive material. In this regard, the crossing line shield wall formed from the fourth layer of electrically conductive material is formed to overlie the crossing line shield wall formed from the third layer of electrically conductive material such that the third and fourth layer crossing line shield walls together define an enclosed area within which the two layer elevated crossing line is located. The method of the present invention may also include the further steps of depositing a fifth layer of electrically conductive material (e.g., doped polysilicon) above the fourth layer of electrically conductive material, and forming an electrical/particle shield from the fifth layer of electrically conductive material. In this regard, the fifth layer electrical/particle shield is formed to overlie the enclosed area defined by the third and fourth layer crossing line shield walls and to be positioned in a spaced relation above the two layer elevated crossing line. Where a two layer elevated crossing line having enhanced rigidity is not needed, the method of the present invention may include the additional steps of depositing a fourth layer of electrically conductive material (e.g., doped polysilicon) above the third layer of electrically conductive material, and forming an electrical/particle shield from the fourth layer of electrically conductive material. In this regard, the fourth layer electrical/particle shield is formed to overlie the enclosed area defined by the third layer crossing line shield wall and to be positioned in a spaced relation above the third layer elevated crossing line.
These and other aspects and advantages of the present invention will be apparent upon review of the following Detailed Description when taken in conjunction with the accompanying figures.